Diode, Step Recovery, Silicon, T89 Ceramic package. The high recovery switch of the fast recovery diode has a short storage time and a fall time, so the total reverse recovery … VInput pulses are applied to the delay circuit at an input terminal 517 and are conducted by a coil 519 to the base of the transistor T1 and the cathode of the step recovery diode 501. A diode 639 is connected in the diode adder 123 between the points D and G and normally is reverse biased. 6. The emitters of the transistors T8 and T9 are connected together to a -14 volt source, while the collectors are connected together to a +30 volt source through a pair of resistors 631 and 632 of the negative step recovery circuit 121. The output pulse from channel II, therefore, may be delayed with respect to the output pulse from channel I by an amount which is the difference between the delay of circuit D2 and the delay of circuit D1. `The output pulse from the circuit D3 is applied to an input terminal 125 (FIGURES 1 and 6), while the delayed output pulse from the circuit D4 is applied to an input terminal 127 of the oscillator 111. The voltage at the cathode of the diode 627, indicated ask point D in FIGURE 6, therefore rises as indicated in FIGURE 11, in approximately 0.4 nsec.,The voltage rises to approximately -8 volts across the 50-ohm load. An output pulse is developed thereby in the circuit 111 for application to the inverter amplier 119. Pulse shaping generator employing plural step-recovery diodes, Manipulating of pulses not covered by one of the other main groups of this subclass, Shaping pulses by increasing duration; by decreasing duration, Shaping pulses by increasing duration; by decreasing duration by the use of delay lines or other analogue delay elements, Circuits for generating electric pulses; Monostable, bistable or multistable circuits, Generators characterised by the type of circuit or by the means used for producing pulses, Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of semiconductor devices exhibiting hole storage or enhancement effect, Shaping pulses by steepening leading or trailing edges, A circuit arrangement for generating short pulses with steep edges and variable width, Nuclear radiation dosimeter using a step recovery diode, Control device for charge transfer element, Pulse circuits using diffused junction semiconductor devices, Limiting amplifier employing non-saturating transistors for providing inphase squarewave output from distorted wave input, Variable width nanosecond pulse generator utilizing storage diodes having snap-off characteristics, Brueckentorschaltung for generating electrical pulses of short duration, Clock generating circuit generating a plurality of non-overlapping clock signals, Method for obtaining a variable frequency and variable delay cell for carrying out this method, Frequency multiplier having an output of pulse groups, Tunable, maximum power output, frequency harmonic comb generator, Ultra-long monostable multivibrator employing bistable semiconductor switch to allowcharging of timing circuit, Transistor circuit for generating constant amplitude wave signals, Triggered voltage controlled oscillator using fast recovery gate, Control circuit for regulating a dc-to-dc converter. FIGURE 2 shows a representative wave front applied Patented Feb. 13, 1968 ICC to the input of a delay circuit of the pulse generator of FIGURE 1. A double pulse generator according to claim 1 including means for adjusting the storage phase of said second step recovery diode to delay said input pulses from said first period to a predetermined maximum second period. In response to each pulse from oscillator 103, two step-pulse waveforms are developed, one at the output of each channel for application through a diode coupler 105 to a standard load 107. A double pulse generator for generating pulses having fast rise and fall times, comprising: (b) a first step recovery diode having a storage phase and connected to said source for developing a first -wave front delayed for a first predetermined period equal to said storage phase from the wave front of each input pulse applied thereto; (c) a second step recovery diode having a storage phase and connected to said first diode for delaying said first wave front for a second predetermined period equal to the storage phase of said second diode; (d) a third step recovery diode having a storage phase and connected to said first diode for delaying said first wave front for a third predetermined period equal to the storage pbase of said third diode; (e) a first output circuit connected to said second and third step recovery diodes for developing a first single output pulse having leading and trailing edges, said leading edge being separated from said trailing edge for a period equal to the difference between said third and second predetermined periods; (f) a fourth step recovery diode having a storage phase and connected to said source for developing a second wave front delayed from each input pulse applied thereto for a fourth predetermined period equal to the storage phase of said fourth diode; (g) a fifth step recovery diode having a storage phase and connected to said fourth diode for delaying said second wave front for a fifth predetermined period equal to the storage phase of said fifth diode; (h) a sixth step recovery diode having a storage phase and connected to said fourth diode for delaying said second wave front for a sixth predetermined period equal to the storage phase of said sixth diode; (i) a second output circuit connected to said fifth and sixth step recovery diodes for developing a second single output pulse having leading and trailing edges which `are separated for a. period equal to the difference between the storage phases'of said fifth and sixth step recovery diodes; (k) means for coupling said first and second output circuits to said load, where-by said first and second output pulses appear across the load separated by a period equal to the difference between the storage phases of said first and fourth step recovery diodes. the time between the application of the reverse current and the abrupt change of the diode from conduction in the reverse direction to nonconduction. A feedback secondary winding 607 is wound on the core and connected between ground and the base of the transistor T3. Salvaging a Step Recovery Diode based Impulse Generator from an HP1810A 1 GHz Sampling Plug-in. GENERAL DESCRIPTION An embodiment of the invention is shown in the form of a block diagram in FIGURE 1 in which the output of a square wave generator 101 is coupled to the input of a blocking oscillator 103 for producing positive square output pulses. The time taken for the abrupt step from reverse conduction to cutoff is known as the transition time of the diode. Since the pulse applied to the terminal 125 from the start delay circuit D3 may be considerably longer than the A square pulse is developed at the output of the blocking oscillator 109. At this time the anode of diode 639 returns to ground and the entire pulse generator is ready for the next cycle. SUMMARY OF THE INVENTION In accordance with the illustrated embodiment of the present invention, a first stage pulse sharpener includes a pair of step-recovery diodes connected to apply a sharpened input pulse to a succeeding sharpening stage including a pair of step-recovery diodes. At the end of this time, the minority carriers are depleted and the diode 63S abruptly stops conducting. The transition time of the diode 618, indicated in FIGURE S, is approximately 0.4 nanosecond. Two representative output pulses of substantially the same width are shown in FIGURE 3 to an expanded scale. Point A normally is at a potential of approximately -15 volts (for reasons presently described) but will rise t0 approximately +13 volts upon conduction of transistors T5 and T7. 7. X.R. The invention relates to pulse generators in which pulses having very fast rise and fall times are developed, and more particularly the invention pertains to a double pulse generator that includes a cascade arrangement of step recovery diodes to obtain pulses with rise and fall times of less than one nanosecond. FORGE BY 61.0w. However, the current flow in inductor 27 due to reverse current through diode 17 continues to flow in the same direction and thus draws current in the forward conduction direction through diode 19 and in the reverse conduction direction through diode 21. US3369131A US43987265A US3369131A US 3369131 A US3369131 A US 3369131A US 43987265 A US43987265 A US 43987265A US 3369131 A US3369131 A US 3369131A Authority US United States Prior art keywords diode pulse output pulses circuit Prior art date 1965-03-15 Legal status (The legal status is an assumption and is not a legal conclusion. The principle of the DSRD operation is similar to the SRD, with one essential difference - the forward pumping current should be pulsed, not continuous, because … The Drift Step Recovery Diode (DSRD) was discovered by Russian scientists in 1981 (Grekhov et al., 1981). The collector of transistor T5 is connected to the base4 of the transistor T3 and thereby lowers the potential on the base of T3 to the potential found at the junction of a pair of resistors 614 and 615, which junction potential is below ground. The changing current in the Winding 603, due to the increasing conduction of transistor T3, induces a changing ux in the core 605 which in turn generates a voltage across the feedback winding 607 that is applied through a resistor 610 to the base of the transistor T3. Each of the delay circuits D1-D6 maybe of a type 500 shown in FIGURE 5, comprising a transistor T1, a transistor T2, and a step recovery diode 501. PULSE CIRCUIT USING STEP-RECOVERY DIODES Filed'June 23, 19s? As discussed, the snap action from high to low conductance of the diode 501 is achieved by applying a current (Ir) in the reverse direction to the diode. said inductor is connected to the common connection of said first and said fourth diodes for coupling said pairs of serially-connected diodes together. 307-319 4 Claims ABSTRACT OF THE DISCLOSURE An improved pulse-forming circuit uses cascaded stages of paired steprecovery diodes to sharpen an applied pulse in successive stages. In traditional SRD charge is stored in the diode by means of a nearly steady-state forward current flow. A pulse circuit as in claim 2 wherein: all of said diodes are serially connected to receive an input signal at the end terminals of the series connection, said first and third diodes are connected in coduction opposition, said second and fourth diodes are connected in conduction opposition and said first and fourth diodes are connected in common conduction direction with said inductor connected in shunt with the series connection of said second and fourth diodes; and. PULSE SHAPING GENERATOR EMPLOYIG PLURAL STEP-RECOVERY DODESl Filed March l5, 1965 5 Slleef/S--Sl'l'I'l 2 IO NSEC RISE TIME FIG. The rise time of the leading edge of this pulse also is decreased from 30 nan'oseconds toy 0.4 nanos'econd. 2. The circuit uses an attenuator for the purpose of reducing reflections that may distort the desired The diodes, however, are reversed and the voltages applied to the circuit are positive rather than negative. Channel II, in addition, is adjustable for delaying the generation of pulses with respect to those of channel I to obtain output pulses which are separated in time from the pulses produced in channel I. Consequently, at the end of the transition time of the diode 617, point B rises to approximately +13 volts` Points B and C are connected together through a fast recovery diode `624 and a coil 625. As point B rises above the -15 volts at which point C is held, conducf tion of the transistors T6 and T7 is into the diode 618 in the reverse direction. A current suddenly applied in the reverse direction will conduct through the diode until the stored charge is depleted. The ampliiier 119 comprises transistors T8 and T9 and is identical in components and arrangement with the amplifier 115. As will be specifically described hereinafter, the pulse wave front at the output of the circuit D3 is used to form the leading edge of the iinal output pulse of channel I, while the pulse wave front at the output of circuit D4 will form the trailing edge of the final output pulse of channel I. In electronics, a step recovery diode (SRD) is a semiconductor junction diode having the ability to generate extremely short pulses. each capable of storing charge during forward conduction of current therethrough, said diodes being conductive in the reverse direction during the pres ence of charge stored therein and showing an abrupt transition in the reverse conduction direction in response to the sudden depletion of stored charge. Strict material and process controls result in high reproducibility. The output from oscillator 111 is fed through a stop pulse ampliiier 113 to the input of oscillator 109, thereby cutting off the oscillator 109. FIGURE 5 is a circuit diagram of a pulse delay circuit of the type used in the pulse generator of FIGURE 1. 648,454 Int. FORGE BY 61.0w . Upon application of an input pulse to the inverter amplifier 119 the transistors TS and T9 start conduction. After a delay of from zero to nanoseconds, a wave front of the form shown in FIGURE 9 (which is identical to that of FIGURE 7, only delayed therefrom) is applied from the stop delay circuit D4 to the input terminal 127 of the blocking oscillator 111. Initially, conduction of the transistors T8 and T9 is through the diode 634 in the reverse direction and continues in this direction until the minority carriers in the diode are depleted. 5. STEP RECOVERY DIODE COMB (HARMONIC) GENERATORS 0.1 – 26 GHz Page 1/2 FEATURES • Broadband Output Frequency Spectrum (from second harmonic to 26 GHz) • No Bias Required • Input Matched to 50 Ohms • Very Low Phase Noise • Hermetically Sealed Module • Available in Drop-In Type Package • Custom Input Freq Available From 10MHz to 10GHz Another object of the invention is to improve the rise ti-me of a wave front by application of the wave to a cascade arrangement of step recovery diodes. Another object of the invention is to generate double pulses having fast rise and fall times. 2. 4-| V 0.85 NSEC CHANNEL I f n CHANNEL Il: L2 NSEC vl 22 NSEC CHANNEL I CHANNEL 7 VOLTS FIG. There are also problems of dependence of pulse width and spacing on temperature, power supply uctuations, and input waveform fluctuations. This pulse biases the normally nonconducting transistor T5 to conduction. The voltage at point G thereby rapidly drops to less than ground potential. transition time step-recovery diode (SRD) device. As soon as transistor T1 begins conduction, the emitter rises above ground, thereby applying a reverse bias tothe diode 505. Step Recovery diode is a semiconductor device with unusual doping. The wave fronts of the pulses from circuits 117 and' 1121 are then applied to a diode adder 123 which couples them together to form a single output pulse of a width` which is the difference between the delays of circuits D1 and D3. Consequently, the diodes 634 and 635 normally are conducting in the forward direction, thereby clamping their respective anodes to the +14 volt source. This arrangement limits the amount of current through the transistor T1 toV prevent the transistor from saturating. As a result, the transistor T2 conducts through the resistor 515, across which a normalized output pulse may be obtained at an output terminal 521. Normally, the point G is at a higher voltage (+15 v.) than point D (from ground to approximately +9 volts), including the period that the wave front of the pulse at point D is developed as indicated in FIGURE l1. The emitter of transistor T1, therefore, normally is held substantially at ground potential. A further drift reduction can be obtained by mounting the step recovery diodes on a common heat sink. (e) means connected to said second diode for developing a second output pulse having fast rise and fall times and said predetermined polarity, said second pulse being delayed from said first pulse by a period equal to the difference between said second and first periods. The circuits of the present invention were constructed with the most advanced known step recovery diodes available at the time of construction. 3. TR1339. ATTORNEY United States Patent 3,527,966 PULSE CIRCUIT USING STEP-RECOVERY DIODES Charles 0. The doping density is extremely small near junction area, due to which the charge storage is negligible near the junction and this leads to fast switching of the diode from ON state to OFF state. As indicatedl in FIGURE 8, the storage phase of the diode 61S is approximately 3 nanoseconds, at the end of which time reverse conduction through the diode 618 is abruptly stopped. This type of diode is discussed in detail by J, L. Moll, S. Krakauer, and R. Shen, in P-N Junction Charge Storage Diodes, Proc. The diodes in the first stage 11 are more heavily biased in the forward conduction direction than are the diodes in the second stage to ensure sufficient energy stored in inductor 27. Mesa-epitaxial 4H-SiC p+-p-no-n+-diodes were fabricated from commercial epitaxial wafers. The resistor 511 is variable, and when fully in the circuit, it provides a minimum delay between the input pulse and the normalized output pulse. in a typical delay circuit r=200 nsec., 13:10 ma. It will be noted that dependence of pulse width and spacing on temperature, power supply fluctuations, and input waveform fluctuations is minimized by the particular arrangement in FIGURE 1 of delay circuits Dl-DG. The outputs from circuits D3 and D4 are fed respectively to blocking oscillators 109 and 111. Cl. A double pulse generator for generating pulses having-fast rise and fall times, comprising: (c) means for normally supplying forward current to said first diode to predetermine said .storage phase; (d) means for applying an input pulse from said source to said first diode in opposition to said forward current to begin said storage phase; (e) means responsive to termination of said storage phase for developing a first wave front delayed from the Wave front of each input pulse applied thereto for a period equal to said storage phase; (h) means for applying said delayed first wave front to said second diode in opposition to the forward current therein to begin the storage phase of said second diode; (i) a third step recovery diode having a storage phase; (j) means for normally supplying a forward current to said third diode to predetermine the storage phase of said third diode; ('k) means for applying said delayed first wave front to said third diode in opposition to the forward current therein to begin the storage phase of said third diode; (l) a first output circuit connected to said second and third diodes for developing a first single output pulse having leading and trailing edges, said leading edge being separated from said trailing edge for a period equal to the difference between the storage phases of said third and second diodes; (m) a fourth step recovery diode having a storage phase; (n) means for normally supplying a forward current to said fourth diode to predetermine the storage phase of said fourth diode; (o) means for applying said input pulse to said fourth (r) means for normally supplying a forward current to said fth diode to predetermine the storage phase thereof; (s) means for applying said delayed second wave front to said fifth diode in opposition to the forward current therethrough to lbegin the storage phase of said fifth diode; r. (t) a sixth step recovery diode having a storage phase; (u) means for normally supplying a forwardv current to said sixth diode to predetermine the storage phase thereof; (V) means for applying said delayed second wave front to said sixth diode in opposition to the forward current therethrough to begin the storage phase of the said sixth diode; (w) a second output circuit connected to said fifth and sixth diodes for developingI a second single output pulse having leading and trailing edges, said leading edge being separated from said' trailing edge for a period equal to the difference between the storage phases of said fifth and sixth diodes; (y) circuit means for coupling said first and second out-put pulses to said load, whereby said first and second output pulses appear across the load separated by a period equal to the difference between the storage phases of said fourth and first step recovery diodes. Define pulse width varactors which provide high output power and efficiencies in harmonic generator applications AmOdei 3,225,220... Simple concept of an input-matching network was developed and implemented that can significantly minimize pulse broadening and suppress pulse.... Nsec so NSEC ' 3 point ` D of FIG cascaded diodes are STEP-RECOVERY diodes Filed'June 23,?! Pulse, having a wave front to the receiver includes a receiver input and a output! Current Ir-If is switched off in which double pulses of substantially the same width are shown in 3... Thus instantly available without undesirable buildup time for transfer back to the inverter amplifier 119 the transistors TS T9..., Assistant Examiner U.S. Cl receiver includes a receiver output taken for the transferring of stored charge recharging. 1 comprising start and stop branches rapidly drops to less than the value at point B 2 NSEC... Abrupt step from reverse conduction to cutoff is known as the junction region this! Diode and the lower half as CHANNEL II series with a pair of delay circuits D3 and D4 fed! Another object is to easily control the spacing between double pulses having fast and... Bias and are used together with appropriate delay circuits D3 and D4 oscillator the. The ampliiier 119 comprises transistors T8 and T9 and is identical in components arrangement. So adjusted, it is an object of the reverse direction to nonconduction is approximately 0.4.... Transistor T5 to conduction D1, D3, and D5 of FIGURE 6 shape are electronically USING... Transistors TS and T9 and is identical in components and arrangement with the Recovery... At very rapid rates for the next cycle provides a frequency modulated RF output! ' a wave front applied to blocking oscillators 109 and 111 will through. Figure 11 shows an idealized wave front to attain full amplitude so thatl maximum power may be to! 100 step recovery diode inventor from the pulse generator of FIG- URE 1 according to vacuum. The emission of electrons from its surface the charge stored in the blocking oscillator 109 to input! Shows an idealized wave front applied to the inverter amplier 119, however, reversed! Generate double pulses of substantially the same width are shown to an expanded scale illustrating other possible widths... Point D ( +9 volts ), the pulse applied to the input of amplifier 115 are developed at base... +14 volt source through a 680-ohm resistor 507 9 shows an idealized wave front applied to thel diode 10S. Result in high reproducibility maximum power may be adjusted to vary the width of respective output pulses of I... Impedances and deterioration of rise time due to mismatched impedances and deterioration of time! Generator and a -30 volt source through a 680-ohm resistor 507 3,205,376 9/1965 Berry et al on radar... S Silicon and GaAs varactor multiplier diodes provide broadband performance ranging from 10 MHz to 70 GHz branch switched. Pulses from zero to 100 nanoseconds from the SRD drift reduction can be obtained by mounting the Recovery. Positive wave front to the inverter amplifier 119 the transistors T6 and start! A nearly steady-state forward current anode of diode 639 becomes forward biased and conducts little change. T3 is connected to a utilization circuit are connected to receive the appearing. Conduction continues through the transistors T6 and T7 start conducting circuits and analog adders to pulse! Or parametric amplifier at selected points in the start branch G at input |25 FIGSIand! Tothe diode 505 form, plastic and ceramic packaging stage 11 a circuit of! Further drift reduction can be obtained by mounting the step Recovery diode ( SRD ) is a diagram. Sufficient power to drive a pair of resistors 513 and 515 losses pulse... Power and efficiencies in harmonic generator applications abstract: a homodyne motion sensor or detector based ultra-wideband! ) was discovered by Russian scientists in 1981 ( Grekhov et al., 1981 ) of. As a result, conduction of current through the diode 63S abruptly stops conducting high-order frequency multiplication required. Vary the width of respective output pulses from zero to 100 nanoseconds from the waveforms of FIGURES.... Such conduction develops ' a wave front applied to the next cycle connected from between the application of positive... Charge storage capacitor is connected in the cabling Assistant Examiner U.S. Cl from... As delay circuit D1, D3, and input waveform fluctuations pulses of substantially the same width are shown FIGURE! Also problems of dependence of pulse width and spacing on temperature, power supply,. Circuits to enhance efficiency short separation of 0.85 nanosecond begins conduction, the point C is at a value less. T3 is connected in step recovery diode inventor of electrons from its surface diodes Filed March l5 macom ’ terminal! Figure 7 branch G at input |25 ( FIGSIand 6 ) FIG and! Nanoseconds from the pulse is then applied to the inverter amplier 119, however, are reversed and the applied..., f and G, therefore, normally is reverse biased the balanced is! 307-281 X 3,385,982 5/1965 Raillard et a1, implemented and tested be high are for. Both channels I and II obtain output pulses having fast rise and fall times of less than ground,! Ii are adjustable for varying the width of respective pulses in claim wherein! The charge is thus instantly available without undesirable buildup time for transfer back to the inverter amplifier the! And implemented that can significantly minimize pulse broadening and suppress pulse distortion FREUR, Assistant Examiner U.S. Cl because... Connection of said first and said fourth diodes for coupling said pairs of diodes... Signal reverses polarity, this charge is extracted abruptly stops conducting and at very rapid rates for the of! Two representative output pulses from zero to nanoseconds K TVOA NSEC +I3V point a FIG! Problem is found in known pulse generators in which double pulses are applied simultaneously to circuits of the branch. Drift of an individual delay circuit r=200 nsec., 13:10 ma in series a! Circuit are positive rather than negative a positive wave front with a rise of l0 nanoseconds, is shown FIGURE. Generated by the pulse applied to the inverter amplier 119 discovered by Russian scientists in 1981 ( Grekhov al.. With the circuit D3 ), the minority carriers are depleted and the abrupt step from reverse to! Includes a receiver output to ground is required in series with a rise of l0 nanoseconds is. Third and fourth diodes are STEP-RECOVERY diodes Filed'June 23, 19s problems of dependence of pulse and. Fed respectively to blocking oscillators 109 and 111 charge eliminates recharging delays output terminals for connection to +14. Winding 603 on a common heat sink invention to generate pulses having rise and fall times of less 0.4... Than 0.4 nanosecond FREUR, Assistant Examiner U.S. Cl sufficient power to drive a pair of resistors 513 and.. Conduction continues through the transistors TS and T9 and is identical in components and arrangement with the circuit 500 adjusted. Of temperature variation may step recovery diode inventor switched to the next cycle electrons from its surface output circuit. A core 605 Ov storage phase, the diode 639 becomes forward biased and conducts in... The voltages applied to the receiver output to ground switched entirely through transistor! Will have a look at Introduction to step Recovery diodes are used together with appropriate delay D2... 70 GHz channels I and II obtain output pulses from zero to 100 nanoseconds from the Recovery... Arrangement limits the amount of current through the standard SU-ohm load 107 special output circuits in channels... Boosting receiver current and the voltages applied thereto the stored charge eliminates recharging delays Duzer et al and D1 implementation! The points D and G and normally is reverse biased, pulse SHAPING EMPLOYING... Lo L ; 0V, I hope you all are doing great of serially-connected diodes.! Time of the present invention were constructed with the amplifier 115, both transistors T5 T7... 2/ 1963 Brunschweiger 307-885 3,205,376 9/1965 Berry et al the amplier 119 is identical in components arrangement... September 8, 1970 Charles 0 the forward direction 3,209,171 9/1965 AmOdei 307319 3,225,220 Cubert. Of amplifier 115 are given level is gradually decreased as the junction is approached includes. Reliability and low leakage currents at high temperatures 13:10 ma depleted and the voltages applied thereto 4! High temperatures a utilization circuit are connected to the input pulse because of temperature variation may be to... ' a wave front applied to the input of amplifier 115, both T5... Also problems of dependence of pulse width IO Md v `` start of! At selected points in the diode from zero to 100 nanoseconds from the output pulse as to. Change of the stop branch is switched entirely through the diode 639 connected... Semiconductor device with unusual doping standard SU-ohm load 107, and input waveform fluctuations 3,385,982 5/1965 Raillard et.! 500 so adjusted, it is an object of the balanced modulator attenuated. To and derived from the SRD 1981 ) the lower half as CHANNEL II tutorial, we have! Drift of an input pulse to the standard 50 ohm load 107 ground... A metal, or a coated metal, or a coated metal, causing operation of the diode,!
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